module sel_driver (
    input clk,
    input rst_n,
    input [23:0] dis_data,           // 计数器模块传递过来的数据
    output reg [5:0] sel,       // 片选
    output reg [7:0] dig        // 段选
);
    
    parameter   ZERO = 7'b1000000,
                ONE =  7'b1111001,
                TWO =  7'b0100100,
                THREE =7'b0110000,
                FOUR = 7'b0011001,
                FIVE = 7'b0010010,
                SIX =  7'b0000010,
                SEVEN =7'b1111000,
                EIGHT =7'b0000000,
                NINE = 7'b0010000,
                A    = 7'b0001111, // 正号
                B    = 7'b0111111;  // 负号



    parameter TIME_20US = 1000; 




    reg dot; // 小数点

    reg [3:0] data ; // 寄存时分秒

   
    
/************************************ 20us ************************************/
    reg [9:0] cnt;   
    wire add_cnt;
    wire end_cnt;

    always @(posedge clk or negedge rst_n) begin
        if(!rst_n) cnt <= 0;
        else if( add_cnt) 
            if(end_cnt) cnt <= 0;
            else cnt <= cnt + 1'b1;
        else
            cnt <= cnt;
    end
    assign add_cnt = 1'b1;
    assign end_cnt = add_cnt && cnt == TIME_20US - 1;
/************************************ 20us ************************************/
 

/************************************ 每20us 片选-段选 的移动 ************************************/
    always @(posedge clk or negedge rst_n)begin

        if(!rst_n)          sel <= 6'b011_111;
        else if (end_cnt)   sel <= {sel[0], sel[5:1]};
        else                sel <= sel;

    end
/************************************ 每20us 片选-段选 的移动 ************************************/


    always @(posedge clk or negedge rst_n) begin
        
        if(!rst_n) 
            begin
                dot <= 1'b1;
                data <= 4'hf;        
            end
        else
            case(sel)
                6'b011_111: begin dot <= 1'b1; data <= dis_data[3:0];  end
                6'b101_111: begin dot <= 1'b1; data <= dis_data[7:4];  end
                6'b110_111: begin dot <= 1'b1; data <= dis_data[11:8];  end
                6'b111_011: begin dot <= 1'b0; data <= dis_data[15:12]; end
                6'b111_101: begin dot <= 1'b1; data <= dis_data[19:16];  end
                6'b111_110: begin dot <= 1'b1; data <= dis_data[23:20];  end
                default: begin dot <= 1'b1; data <= 4'hf; end
            endcase
    end


    always @(posedge clk or negedge rst_n) begin
        if(!rst_n) dig <= 8'hFF;
        else 
            case(data)
                4'h0: dig <= {dot,ZERO};
                4'h1: dig <= {dot,ONE};
                4'h2: dig <= {dot,TWO};
                4'h3: dig <= {dot,THREE};
                4'h4: dig <= {dot,FOUR};
                4'h5: dig <= {dot,FIVE};
                4'h6: dig <= {dot,SIX};
                4'h7: dig <= {dot,SEVEN};
                4'h8: dig <= {dot,EIGHT};
                4'h9: dig <= {dot,NINE};
                4'hA: dig <= {dot,A};
                4'hB: dig <= {dot,B};
                default: dig <= 8'hFF;
            endcase
    end


endmodule